Microsoft Word - TMAG-MFA-Final

1 Low Power Magnetic Full-Adder based on Spin Transfer Torque MRAM Erya Deng 1,2 , Yue Zhang 1,2 , Jacques-Olivier Klein 1,2 , Dafiné Ravelsona 1,2 , Claude Chappert 1, 2 , and Weisheng Zhao 1,2* 1 IEF, Univ. Paris-Sud, Orsay, 91405, France 2 CNRS, UMR 8622, Orsay, 91405, France *Contact: [email protected] Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on non-volatile memories (NVMs) are being investigated. Spin transfer torque (STT) Magnetic RAM (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance and 3D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements.